View IR3Y48A1_41233.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

BACK
IR3Y48A1
IR3Y48A1
DESCRIPTION
CCD Signal Process & Digital Interface IC
PIN CONNECTIONS
48-PIN QFP TOP VIEW
The IR3Y48A1 is a CMOS single-chip signal processing IC for CCD area sensors which includes correlated double sampling circuit (CDS), clamp circuit, programmable gain amplifier (PGA), reference voltage generator, black level detection circuit, 18 MHz 10-bit analog-to-digital converter (ADC), timing generator for internally required pulses, and serial interface for internal function control and PGA gain control.
48 47 46 45 44 43 42 41 40 39 38 37 NC 1 AVDD4 2 NC 3 VRN 4 VRP 5 AVDD2 6 AVDD2 7 AVSS2 8 AVSS2 9 VCOM 10 CCDIN 11 REFIN 12 13 14 15 16 17 18 19 20 21 22 23 24 CLPCAP ADIN OBCAP MONOUT NC AISET AVDD1 AVSS1 NC ADCK SHR SHD 36 OUTCK 35 RESETN 34 AVDD3 33 AVSS3 32 STBYN 31 CSN 30 SDATA 29 SCK 28 OBP 27 CCDCLP 26 BLK 25 ADCLP
FEATURES
* Low power consumption : 80 mW (TYP.) * Wide gain range : -1.94 to 36 dB (Gain step : 0.047 dB/step) * High speed sample-and-hold circuits : pulse width 11 ns (MIN.) * Independent CDS and PGA gain control - CDS : -1.94/0/6/12 dB - PGA : 0 to 24 dB * Black level canceler - Settling target : 16 to 127 LSB * Capable of independent input of ADC conversion clock and data output clock * Power down mode : less than 1 mW * Built-in serial interface * 10-bit ADC operating up to 18 MHz - DNL : 0.6 LSB (TYP.) * Maximum input level of CCD signals : 1.1 Vp-p * Accepts a direct signal input to ADC or PGA (input level : 1.0 Vp-p (TYP.)) * Single 2.7 to 3.6 V power supply * Package : 48-pin QFP* (P-QFP048-0707) 0.5 mm pin-pitch * Contact SHARP in order to obtain the details of package dimensions of the IR3Y48A1.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
DO9 DO8 DO7 DO6 DO5 DVDD DVSS DO4 DO3 DO2 DO1 DO0
(P-QFP048-0707)
IR3Y48A1
BLOCK DIAGRAM
SHR 23 CLPCAP 13
DC CLAMP
SHD 24 CLPCAP
MONOUT 16
BANDGAP VREF
CCDCLP
REFIN
CDS +
12
S/H
PGA ROUGH
PGA FINE 10-BIT ADC 0 to 6 dB (0.047 dB/STEP)
VRP 5 VCOM 10 4 VRN DO0 to DO9 37 to 41, 44 to 48 19 AVDD1 6,7 AVDD2 34 AVDD3
CCDIN
11 ADCLP -1.94/0/6/12 dB
CCD ADIN 14 OBCAP 15
0/6/12/18 dB
DAC
COMPARE
BLACK LEVEL REGISTER
2 AVDD4 20 AVSS1 8,9 AVSS2 33 AVSS3 43 DVDD 42 DVSS
OBP AISET 18 TIMING GENERATOR SERIAL REGISTER
ADCK 22
26 BLK
28 27 25 31 29 30 OBP CCDCLP ADCLP CSN SCK SDATA
35 RESETN
32 STBYN
36 OUTCK
2
IR3Y48A1
PIN DESCRIPTION
PIN NO. SYMBOL 1 NC 2 3 AVDD4 NC I/O - - -
VDD
EQUIVALENT CIRCUIT
DESCRIPTION No connection. Supply of 2.7 to 3.6 V analog power. No connection. ADC internal negative reference voltage. (Connect to AVSS via 0.1 F.) ADC internal positive reference
4
VRN
O
5
VRP
O
GND
voltage. (Connect to AVSS via 0.1 F.) Supply of 2.7 to 3.6 V analog power. Supply of 2.7 to 3.6 V analog power. An analog grounding pin. An analog grounding pin.
6 7 8 9
AVDD2 AVDD2 AVSS2 AVSS2
- - - -
VDD
ADC internal common reference voltage. (Connect to AVSS via 0.1 F.)
10
VCOM
O
10
GND
CDS circuit data input.
VDD
11
CCDIN
I
CDS circuit reference input. 12 REFIN I
GND
13 14 15 16
CLPCAP ADIN OBCAP MONOUT
O I O
Clamp level output.
VDD
(Connect to AVSS via 0.1 F.) ADIN signal input. Black level integration voltage. (Connect to AVSS via 0.1 F.)
O
GND
Monitor output of CDS or PGA.
Internal FET gate
3
IR3Y48A1
PIN NO. SYMBOL 17 NC I/O -
VDD
EQUIVALENT CIRCUIT
DESCRIPTION No connection. Internal analog circuit bias current input. (Connect to AVSS via 4.7 k$.)
18
AISET*
I
18
GND
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
AVDD1 AVSS1 NC ADCK SHR SHD ADCLP BLK CCDCLP OBP SCK SDATA CSN STBYN AVSS3 AVDD3
- - - I I I I I I I I I I I - -
VDD GND
Supply of 2.7 to 3.6 V analog power. An analog grounding pin. No connection. ADC sampling clock input. Reference sampling pulse input.
VDD
Data sampling pulse input. Pulse input for ADIN clamp and black calibration control. Blanking pulse input. Clamp control input. Black level period pulse input. Serial port clock input. Serial port data input. Serial port chip selection (active at low). Power down control (power down at low). An analog grounding pin. Supply of 2.7 to 3.6 V analog power. Reset signal input (reset at low).
35
RESETN
I
Clock input for ADC output. 36 OUTCK I
GND
* High-Z at power down Internal FET gate
4
IR3Y48A1
PIN NO. SYMBOL 37 38 39 40 41 42 43 44 45 46 47 48 DO0* DO1* DO2* DO3* DO4* DVSS DVDD DO5* DO6* DO7* DO8* DO9* I/O O
VDD
EQUIVALENT CIRCUIT
DESCRIPTION ADC digital output (3 state) (LSB). ADC digital output (3 state). ADC digital output (3 state). ADC digital output (3 state).
GND
O O O O - - O
VDD
ADC digital output (3 state). A digital grounding pin. Supply of 2.7 to 3.6 V digital power. ADC digital output (3 state). ADC digital output (3 state). ADC digital output (3 state). ADC digital output (3 state).
GND
O O O O
ADC digital output (3 state) (MSB).
* High-Z at power down
NOTE : NC pins are not connected internally, but recommended to be connected to AVSS.
5
IR3Y48A1
FUNCTIONAL DESCRIPTION Outline
The configuration of the IR3Y48A1 is described below.
SHR SHD MONOUT OUTCK
IR3Y48A1
Clamp VREF
REFIN CCDIN CCD ADIN
Black Control
CDS
+
PGA
10-bit ADC
DO0 to DO9
ADCK
Timing Generator
Serial Register
BLK
OBP CCDCLP ADCLP
CSN
SCK
SDATA
GENERAL TIMING
CCD OB ADCK Effective Pixel (OB) Blanking
BLK
OBP
CCDCLP
OUTCK
DO0-DO9
Data Output
Black Code
NOTE : In this chart, the cycles of the OBP and CCDCLP show the same timing. But the OBP
and CCDCLP can be input at different timing.
6
IR3Y48A1
CDS (Correlated Double Sampling) Circuit
Connect the signal from a CCD sensor to the CCDIN pin via a capacitor and connect the REFIN pin to AVSS via a capacitor. The CDS circuit holds the CCD precharge (reference) level at SHR pulse, then it samples the CCD pixel data at SHD pulse. Correlated (common) noise is removed by the subtracting
precharge level from the pixel data level. CDS can choose a gain setting from 0, 6.02, 12 or -1.94 dB (Mode (3) Register D4 & D5 bits). A CDS gain is controlled separately from a PGA gain. To reduce noise as much as possible, it is recommended to increase the CDS gain first before increasing the PGA gain.
CDS Circuit
Reference Clock (SHR)
Data Clock (SHD)
REFIN CDS
CCD
CCDIN
CDS Output = V (CDS) = V (Data) - V (Precharge)
CDS Operation
Reset Pulse Reset Pulse
V (Precharge) V (CDS) V (Data)
SHR SHD SIG
MAX. Level SHR SHD
SIG fSMAX = 18 MHz/tSMIN = 55 ns
7
IR3Y48A1
Clamp Circuits
DC CLAMP DC level of the CCDIN/REFIN input is fixed by internal DC clamp circuit. DC level of C-coupled CCD signal at the CDS input is set to CLPCAP by
the internal DC clamp circuit. Normally clamp switches are turned on at the black level calibration period. Place 0.1 F external capacitance between CLPCAP and AVSS.
DC Clamp
SHR SHD CCDCLP
Clamp Timing
CCD
Timing Control
(Register Conditions)
REFIN
ADCK
CCD CCDIN
(CCDCLP)
Clamp Source CLPCAP
CCDCLP
CLPCAP Level
DC Clamp Function
CLPCAP
REFIN, CCDIN Clamp Level
NOTE : For ADIN input, clamp operation is controlled by ADCLP.
(Black level calibration is performed at the same time.)
CLAMP OF THE ADIN SIGNAL Clamp operation for the ADIN path is also available. Note that clamp voltage [CLPCAP] is different between CCDIN/REFIN input and the ADIN input. Clamp operation of ADIN signal can be turned off by register setting. Clamp circuit is controlled by ADCLP signal at "ADIN signal to ADC" mode. Black level calibration circuit is also controlled by ADCLP at "ADIN signal to PGA" mode. CLAMP CONTROL Following items are selectable by the register setting. a) Clamp current [Mode (2) Register D7] Normal or fast clamp is selectable for charge current. (Select normal clamp in general.) b) Clamp target [Mode (2) Register D5 & D4] Input signals (REFIN and CCDIN) to be clamped are selectable. It is also possible to turn off the clamp function.
ADIN DC Clamp
ADCLP
Timing Control
ADIN
To PGA or To ADC
(ADCLP)
CLPCAP ADIN DC Clamp Function
8
IR3Y48A1
Black Level Cancel Circuit
The purpose of a black level cancel circuit is to control the DC level of the PGA input so that the ADC output code at a optical black period may correspond to the black level code set up by the register. The black level code of (1 to) 16 to 127 LSB (default : 64 LSB) is available. A black level cancel loop is established while the OBP pin is active. In this loop, the ADC output code is compared with the black level code and the voltage of the OBCAP capacitor is controlled by the result. Thus, the OBCAP voltage settles gradually, and the signal level of the optical black period corresponds to the established value. The charge of the OBCAP capacitor is reset under
following conditions : q Set the black level reset register to "1". [Mode (1) Register D1 = 1] w Set the RESET pin to low. e Power down (by the STBYN pin or register control) The DC clamping [CCDCLP] is allowed while the OBP pin is low. The black level cancellation is also available in "ADIN signal to PGA" mode. (See the broken line path of "Black Level Calibration" below.) The black level cancellation is available at the ADCLP period in this mode. (That means a clamping and a black level cancelling are done simultaneously.)
CDS REFIN CCDIN ADIN OBCAP
S/H
PGA Rough +
PGA Fine 10-bit ADC DO0 to DO9
DAC OBP (Path for ADIN) OBP ADCLP ADCLP
Compare Black Level Register
Black Level Calibration
Blanking CCD
Effective Pixel Signal
Optical Black Period
Blanking
Effective Pixel Signal
ADCK
OBP
OBCAP
Previous Black Level
Resulting Black Calibration Level (Hold)
Black Level Calibration Timing
9
IR3Y48A1
High-speed Black Level Cancellation
The IR3Y48A1 has the function that settles a black level at high speed. The function that increases a settling speed in a fixed period from the access to the serial interface can become available by the register setting. This function increases the gain of the settling DAC in a fixed period, and it increases the charge/discharge current to the OBCAP capacitor. The black level boost function is set with the Mode (3) register, D3, D2, D1 and D0 bits. The default setting is always low gain (D3 = D2 = D1 = D0 = 0). By setting the register D2, D1 and D0 bits, the gain becomes high during 1 to 7 times of OBP pulse period after any access to the serial interface. After that period, the gain returns to low. When setting D3 to "1", the gain is always high. The CSN signal becomes the starting point of the OBP pulse count. The right figure of "Black Loop Settling Gain Boost Timing" is the timing chart when the boost control is on and the boost period is set to 3. The left figure of "Black Level Settling" below is the image of the settlement when the gain is high or low. Black Level Boost
CDS + OBP OBCAP DAC IDAC Low Gain : Small High Gain : Large Compare PGA 10-bit ADC D0 to D9
Black Level Register
Black Loop Settling Gain Boost Timing
CSN TSUCS THCS OBP Counter Black Loop Gain
0 1 2 3 3 0 1 2 0 1 2
High gain
Low gain
High gain
Gain boost function ON (Mode (3) D3 = 1) High gain for 3 pulses (Mode (3) D2 = 0, D1 = 1, D0 = 1)
CSN OBP CSN OBP DOUT Black Code Black Offset High Gain
(Change Register Value)
Area CCD
Low Gain Black Level Target Value
Black Level Settling
CSN & OBP TIMING
PARAMETER CSN setup time CSN hold time SYMBOL TSUCS THCS CONDITIONS MIN. 0 5 TYP. MAX. UNIT s clock
10
IR3Y48A1
Gain Control Circuit
The total gain for a CCD input signal covers from -1.94 to +36 dB. This range consists of CDS (0/6/12/-1.94 dB), PGA
rough (0/6/12/18 dB), and PGA fine (0 to 6 dB (0.047 dB/step)). The CDS gain is controlled by a 2-bit register and the PGA gain is controlled by a 9bit register.
PGA Gain Control
Total Gain Total Gain 36 dB 0.047 dB 30 dB 1 step 24 dB CDS gain = 0 dB (D5 = 0, D4 = 0) CDS gain = -1.94 dB (D5 = 1, D4 = 1) 18 dB CDS gain = 12 dB (D5 = 1, D4 = 0) CDS gain = 6 dB (D5 = 0, D4 = 1)
24 dB
12 dB
6 dB
0 dB 000
511 (Decimal)
0 dB -1.94 dB
000 PGA Gain Setting
511 (Decimal)
CDS Gain Mode (3) Register (D5 & D4) 0/6/12/-1.94 dB
PGA Gain
Rough (0/6/12/18 dB)
Fine 0.047 dB/Step (0 to 6 dB)
to ADC
CCDIN
ADIN (PGAIN)
Total Gain = -1.94 to +35.91 dB
NOTE :
* The gain of the ADIN (PGA) input pass can be set from 0 to 24 dB.
Gain Control
11
IR3Y48A1
A/D Converter Circuit
The IR3Y48A1 integrates an 18 MHz 10-bit full pipeline A/D converter (ADC). This ADC converts following signals : 1. The signal from the CCDIN input through a CDS and a PGA 2. The signal from the ADIN input through a PGA at the ADIN (PGA input) mode. 3. The signal from the ADIN input at the ADIN (ADC input) mode. A/D CONVERSION RANGE The analog input range of the ADC is determined by the internal reference voltage. The full scale of the ADC is 1.0 Vp-p (single end).
HIGH-Z CONTROL OF ADC DIGITAL OUTPUT ADC digital outputs become High-Z under following conditions : q Set the ADC output bit to "1". [Mode (1) Register D2 = 1] w Set the SYBYN pin to low. e Set the power control bit to "1". [Mode (1) Register D0 = 1]
ADC Data Output (Coding : Straight Binary) A/D INPUT MSB DIGITAL OUTPUT CODE LSB
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Full scale 1 1 1 1 1 : 1 0 0 1 0 1 0 1 0 1 : 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1
A/D CONVERTER OUTPUT CODE (AT MODE (1) REGISTER D5 = 1) The format of an ADC digital output is a straight binary. Thus, when input a zero reference voltage, the output code is "all 0", and when input a full scale voltage, the output code is "all 1". CLOCK, PIPELINE DELAY, DIGITAL DATA OUTPUT TIMING The ADCK input is used for an A/D conversion. The ADC input signal is sampled at the falling edge of the ADCK input and 10-bit parallel data is output at the rising edge of the ADCK input after 5.5 clocks of pipeline delay.
: : : : Zero scale
12
IR3Y48A1
Miscellaneous Functions
ADC DIRECT INPUT (ADIN MODE) The direct input path to the ADC or the PGA becomes available by register setting. The selectable paths are shown below : 1. Function disable (default) [Mode (1) Register D5 = 0, D4 = 0]
2. ADIN input to the PGA [Mode (1) Register D5 = 0, D4 = 1] 3. ADIN input to the ADC [Mode (1) Register D5 = 1, D4 = don't care] At the ADIN mode, the BLK, SHD and SHR inputs are ignored.
(N) ADIN
(N + 1)
(N + 2)
ADCK (When ADCK is inverted, signal (N) is sampled by this edge.) ADCLP
Black Cancel & Clamp
DO0-DO9
N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1
N
NOTE : This figure shows the timing when an OUTCK input function is disabled (Mode (1) D8 = 0). When it is enabled (D8
= 1), the data is output at the rising (D7 = 0) or the falling (D7 = 1) edge of the OUTCK input. When ADCLP input is low, both black level cancel and clamp are active at the PGA input mode, and only the clamp is active at ADC input mode.
ADIN Signal Processing (PGA Input)
The operation at ADC direct input is shown below. Thus, the clamped level at the ADCLP timing becomes a reference (CLPCAP at the figure
below), and the ADIN input dynamic range is +1.0 V (TYP.) from the reference level.
Full Scale
CLPCAP + 1.0 V ADC Dynamic Range = 1.0 Vp-p
ADIN
CLPCAP Zero Scale ADCLP Clamp ON
ADIN Signal Input Level
13
IR3Y48A1
POWER DOWN MODE The power down mode can be set either by register setting or STBYN pin. If one of them is set, the IR3Y48A1 powers down. ("OR" logic) MONITOR OUTPUT By setting the register [Mode (2) Register D1 & D0], the signal from MONOUT is selectable. Alternatives are OFF, CDS output, PGA output, or REFIN/ CCDIN output. Note that the gain of the MONOUT pin is fixed to 0 dB regardless the setting of gain control register when the CDS output is selected. The output level of MONOUT is shown below. The MONOUT level becomes VCOM at zero reference level. The signals are output in reverse for the CCD input.
CCD V0 = No signal V1 V2
V3 V3'
MONOUT
V0 = No signal level Monitor reference level = VCOM
V1'
V2'
Monitor Output Level
POLARITY INVERSION The following input polarities can be inverted by register setting : q ADCK (A/D converter sampling clock) [Mode (1) Register D6]
w SHR and SHD (CDS sampling clock) [Mode (2) Register D3 & D2] e BLK, OBP, CCDCLP and ADCLP (Enable controls) [Mode (2) Register D3 & D2]
14
IR3Y48A1
Power Control
Usually, make the power control register (Mode (1) Register D3) "1" to select low power mode. The default setting of this register is "1".
Serial Interface Circuit
The internal registers of IR3Y48A1 are controlled by the 3-wire serial interface. The data is a 16-bitlength serial data that consists of a 2-bit operation code, a 4-bit address, and a 10-bit data. The each bit is fetched at the rising edge of the SCK input and the data is executed at the rising edge of the CSN input. When not access, make the CSN input high. It is prohibited to write to a non-defined address. When a data length is below 16-bit, the data is not executed.
Data Output Clock
The ADCK input or the OUTCK input is selectable as an ADC data output clock.
General Notice for Power Supply
It is recommended to supply power to both AVDD and DVDD from a single regulator. (Keep the absolute maximum rating; DVDD (AVDD + 0.3 V) even at the power-up or the powerdown sequence.) Refer to "APPLICATION CIRCUIT EXAMPLE" for power supply decouplings.
CSN
0 SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SDATA
O0
O1
A0
A1
A2
A3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Op Code
Address
Data
Op code is always ineffective (don't care).
Serial Interface Write Control
15
IR3Y48A1
Registers
The IR3Y48A1 has 10-bit x 7 registers to control its operations. Two of the seven registers are used for Register Map
R/W ADDRESS A3 A2 A1 A0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 REGISTER NAME
the LSI testing. All registers are write only. The serial registers are written by the serial interface.
MAJOR FUNCTIONS [DATA] DOUT timing control/OUTCK polarity/ADCK polarity/ADIN connection/Power control/ADC output/Black level reset/Power down Clamp current/ADIN clamp/Clamp target/ S/H, enable logic/Monitor selection CDS gain control/Black loop gain boost/Boost period PGA gain ADC code at black level (1 LSB step) Test mode (1) (ADIN coupling mode) Test mode (2)
W W W W W W W
0 Mode (1) 1 Mode (2) 0 Mode (3)/CDS gain 1 PGA gain 0 Black level 0 Test (1) 1 Test (2)
1. Register name 2. Register address [Write] 3. Register bit assignment
Mode (1)
A3 A2 A1 A0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Functions DOUT timing control OUTCK polarity ADCK polarity ADIN connection Power control ADC output Black level reset Power down X 0 <-> <-> <-> <----> <-> <-> <-> <-> 0 0 0 0 0 0 0 0
16
IR3Y48A1
4. Register operations
CONTROLS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DOUT timing control OUTCK polarity ADCK polarity ADIN connection 0 1 0 1 0 1 0 0 1 Power control ADC output Black level reset Power down 0 1 X 0 1 0 1 0 1 OPERATIONS DOUT synchronizes to ADCK DOUT synchronizes to OUTCK DOUT changes at OUTCK rising edge DOUT changes at OUTCK falling edge Normal operation as timing chart ADCK clock inversion ADIN function OFF ADIN signal to PGA ADIN signal to ADC Not recommended Low power Normal operation [ADC data output] ADC output High-Z [or logic of STBYN] Normal operation Black level reset [or logic of RESETN] 0 Normal operation 1 Power down [or logic of STBYN]
X : Don't care 4. Black level integral CAP [OBCAP] is discharged if the following case is true. Case 1 : Set "Black level reset" bit to "1". Case 2 : Set RESETN pin to low.
NOTE
1 1
2 3 4
NOTES :
1. DOUT edge control is effective when D8 = 1 (DOUT synchronizes to OUTCK). 2. Power control bit (D3) must be "1" to operate as specified value. The default value is "1" (low power). 3. ADC output is set to high impedance if one of the following case is true. Case 1 : Set "ADC output" bit to "1". Case 2 : Set STBYN pin to low. Case 3 : Set "Power down" bit to "1".
17
IR3Y48A1
1. Register name 2. Register address [Write] 3. Register bit assignment
Default Functions Clamp current ADIN clamp Clamp target S/H, enable logic Monitor selection <-> <-> <----> <----> <---->
X : Don't care
Mode (2)
A3 A2 A1 A0 0 0 0 1
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XX00000000
4. Register operations
CONTROLS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Clamp current ADIN clamp Clamp target 0 1 0 1 0 0 1 1 S/H, enable logic 0 1 0 1 0 0 1 1 Monitor selection 0 1 0 1 0 0 1 1 OPERATIONS Normal clamp (50 A) Fast clamp (100 A) Clamp operation active for ADIN No clamp for ADIN Normal mode [Clamp both REFIN and CCDIN] Clamp REFIN only Clamp CCDIN only Clamp OFF Normal operation as timing chart S/H control polarity inversion Enable control polarity inversion Both of S/H and enable inversion 0 Monitor OFF 1 CDS signal to monitor 0 PGA output monitor 1 Output REFIN and CCDIN (for calibration) 3 4 1 2 NOTE
NOTES :
1. 2. 3. 4. The S/H signals are SHR and SHD. The enable controls are BLK, OBP, CCDCLP, and ADCLP. At this mode, monitor output gain = 0 dB regardless of CDS gain. At this mode, monitor output depends on CDS gain.
18
IR3Y48A1
1. Register name 2. Register address [Write] 3. Register bit assignment
Default CDS gain control Black loop gain boost Boost period D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXXX000000 <----> <-> <------->
X : Don't care
Mode (3)
A3 A2 A1 A0 0 0 1 0
4. Register operations
CONTROLS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CDS gain control 0 0 1 1 Black loop gain boost Boost period 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 OPERATIONS CDS gain = 0 dB CDS gain = +6.02 dB CDS gain = +12.04 dB CDS gain = -1.94 dB Boost control ON Always high gain 0 Always low gain 1 High gain for 1 OBP pulse 0 High gain for 2 OBP pulses 1 High gain for 3 OBP pulses 0 High gain for 4 OBP pulses 1 High gain for 5 OBP pulses 0 High gain for 6 OBP pulses 1 High gain for 7 OBP pulses 1 2 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 NOTE
NOTES :
1. Black loop settling gain is boosted [speed up] for defined period. Gain is boosted n OBP pulse(s) after rising edge of CSN [SIO data write]. Boosted period n (1 to 7 pulses) is determined by "boost period" (D2...D0). After n OBP pulse(s), black loop gain returns automatically to low gain. 2. Black loop settling is always high gain [boosted]. 3. "Boost period" register is effective only when D3 = 1.
19
IR3Y48A1
1. Register name 2. Register address [Write] 3. Register bit assignment
Default Functions PGA gain <------------------------------------>
X : Don't care
PGA gain
A3 A2 A1 A0 0 0 1 1
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X000000000
4. Register operations
D9 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D7 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 CONTROLS D6 D5 D4 D3 0000 0000 0000 0000 0000 0111 0111 1000 1000 1111 0000 0000 1000 1111 0000 0000 1000 1111 0000 0000 1000 1111 1111 D2 0 0 0 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 D1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 D0 0 1 0 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 DECIMAL 0 1 2 3 4 62 63 64 65 127 128 129 192 255 256 257 320 383 384 385 448 510 511 HEX 0 1 2 3 4 3E 3F 40 41 7F 80 81 C0 FF 100 101 140 17F 180 181 1C0 1FE 1FF PGA GAIN (dB) 0.000 0.047 0.094 0.141 0.188 2.916 2.963 3.010 3.057 5.973 6.020 6.067 9.030 11.993 12.040 12.087 15.050 18.013 18.060 18.107 21.070 23.986 24.033
PGA gain
20
IR3Y48A1
1. Register name 2. Register address [Write] 3. Register bit assignment
Default Functions Black level <----------------------------->
X : Don't care
Black level
A3 A2 A1 A0 0 1 0 0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX1000000
4. Register operations
OPERATIONS [ADC CODE : BINARY] B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Black level 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 124 125 126 127 7C 7D 7E 7F 0 0 0 64 40 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 BLACK CODE DECIMAL FORBIDDEN 1 15 16 17 18 19 32 HEX FORBIDDEN 1 F 10 11 12 13 20 NOTE
1 1 1
NOTE :
1. Codes 1 to 15 are available but not recommended. Black calibration period is specified under 15 < code < 128.
21
IR3Y48A1
1. Register name 2. Register address [Write] 3. Register bit assignment
Default Functions ADIN test mode <->
X : Don't care
Test (1)
A3 A2 A1 A0 1 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX0000000
NOTE :
D5 to D0 must always be "0".
4. Register operations
CONTROLS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ADIN test mode 0 1 OPERATIONS Normal operation VCOM centered ADIN for AC coupling
The Test register (D6) is for the AC coupled ADIN input mode. At this mode, the DC bias becomes the VCOM voltage and no clamp signals are required. 1. Register name 2. Register address [Write] 3. Register bit assignment
Default Functions Test modes
Connect a 50 k$ resistor between the ADIN (pin 14) and CLPCAP (pin 13), and input the signal to the ADIN pin via a capacitor.
Test (2)
A3 A2 A1 A0 1 0 0 1
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXXXX00000 <------------------->
X : Don't care
NOTE :
D4 to D0 must always be "0".
22
IR3Y48A1
ABSOLUTE MAXIMUM RATINGS
PARAMETER Power supply voltage Voltage difference Power consumption PD derating ratio Input current Analog input voltage Digital input voltage (Input pin) Digital input voltage (Output pin) Operating temperature Storage temperature SYMBOL AVDD DVDD VDLT PD IIN VINA VINL VONL TOPR TSTG
(AVSS = DVSS = 0 V, all voltages are with respect to GND.)
CONDITIONS RATING -0.3 to +4.5 -0.3 to +4.5 or AVDD + 0.3 DVDD - AVDD TA 25C TA > 25C 0.3 570 4.5 10 AVSS - 0.3 to AVDD + 0.3 AVSS - 0.3 to AVDD + 0.3 AVSS - 0.3 to AVDD + 0.3 -30 to +85 -40 to +125 UNIT V V V mW mW/C mA V V V C C 2 NOTE 1
Except power supply pins
NOTES :
1. The higher voltage of 4.5 V or AVDD + 0.3 V specifies maximum value of DVDD absolute maximum rating. 2. The VONL limits the excess voltage applied to digital output pins.
WARNING :
Operation at or beyond these limits may result in permanent damage to the device. Normal operating specifications are not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS = DVSS = 0 V, all voltages are with respect to GND.)
PARAMETER Analog Supply voltage Digital output SYMBOL CONDITIONS AVDD At start-up, turn on AVDD before (or at DVDD the same time as) turning on DVDD. MIN. 2.7 2.7 TYP. 3.0 3.0 MAX. 3.6 AVDD UNIT V V
ELECTRICAL CHARACTERISTICS Supply Current (NOTE 1)
PARAMETER Supply current at Analog normal operation Digital Supply current at monitor active Supply current at power down SYMBOL IA ID IPE IPD CONDITIONS fs = 18 MHz fs = 18 MHz
(TA = +25C, AVDD = DVDD = 3.0 V)
MIN. TYP. 28 5 30 MAX. 31 7 34 0.1 UNIT mA mA mA mA NOTE 2 2, 3 3 4
NOTES :
1. Specified at a 4.7 k$ AISET resistance. Use a high precision resistor because it influences the supply current. 2. Specified when the monitor function is off. 3. Measured when connecting 10 pF capacitors between the DO0 to DO9 pins and GND, and inputting full scale of 1 MHz sine wave to the ADC. 4. Measured under no analog input and with clock fixed at low.
23
IR3Y48A1
Analog Specifications
(Unless otherwise specified, AVDD = DVDD = 3.0 V, TA = +25C, signal frequency fIN = 1 MHz, signal level = full scale - 1 dB.) The current direction flowing into the pin is positive direction. CDS & CLAMP CIRCUITS
PARAMETER Analog input range Equivalent input noise Input capacitance Input bandwidth Clamp voltage Black calibration time Maximum calibratable offset voltage SYMBOL VICDS VIAI NI CIN CBW VCLPCAP tBKCAL VBKCAL CCDIN input ADIN input 1.65 1.15 1.8 1.3 200 CONDITIONS CCDIN input ADIN input At fs = 18 MHz At max. gain At min. gain CCDIN, ADIN & REFIN
(Sampling frequency fS = 18 MHz)
MIN. TYP. 1.1 1.0 50 200 15 1 1.95 1.45 200 MAX. UNIT Vp-p Vp-p Vrms Vrms pF pixel V V pixel mV 4 5 NOTE 1 2
3
NOTES :
1. The signal dynamic range is below the clamp voltage at the CCDIN input, and it is above the one at the ADIN input. The VICDS is applied at the 0 dB gain. When the gain is below 0 dB, VICDS is 1.25 Vp-p (TYP.). 2. Measured at the MONOUT pin. The noise bandwidth is 100 kHz to 5 MHz. 3. The bandwidth from the CCDIN/REFIN to the ADC. This is defined as the settling time of the ADC when the full scale - 1 dB step input is inputted and the gain is 0 dB. 4. The time that is needed to settle the average value within 1 LSB for the set code when the PGA gain is changed. (The OBCAP capacitor is 0.1 F.) The value of the OBCAP capacitor determines the bandwidth of the black calibration loop. The loop gain is also affected by the operation frequency. Therefore the maximum frequency that is needed to settle within a limited time and the minimum frequency that is needed to avoid the undesirable oscillation are defined corresponding with the external capacitance. Refer to the table below to select the capacitance. OBCAP MINIMUM MAXIMUM FREQUENCY (MHz) CAPACITANCE (F) FREQUENCY (MHz) Within 200 pixels Within 400 pixels 0.068 11 Up to 18 Up to 18 0.1 Up to 18 8 Up to 18 0.15 4 Up to 14 Up to 18 0.33 3 Up to 6 Up to 10 5. The maximum calibratable offset means the difference of the CCDIN reference level and the set data at the OBP period.
24
IR3Y48A1
GAIN
PARAMETER select 0 dB CDS gain select 6.02 dB select 12.04 dB select -1.94 dB Minimum gain PGA input Maximum gain Gain step Total (CDS + PGA) gain monotonicity SYMBOL CONDITIONS GMNN Absolute gain G (1) G (2) G (3) GMNNA GMXNA GSTA ERPA Absolute gain Relative gain Relative gain MIN. -1.9 5.52 11.54 -2.44 -1.3 0 TYP. -0.9 6.02 12.04 -1.94 -0.3 0.047 MAX. 0.1 6.52 12.04 -1.44 0.7 0.094 2 UNIT dB dB dB dB dB dB dB LSB 2 1 NOTE
1
22.906 23.906 24.906
NOTES :
1. Measured at the digital output pins (DO0 to DO9). When the input voltage is 1.0 Vp-p and ADC output is the full scale, the absolute gain is defined as a 0 dB. The relative gain is the relative value from the absolute gain. The gain monotonicity is guaranteed except least significant bit. 2. Measured at the digital output pins (DO0 to DO9).
A/D CONVERTER CIRCUIT
PARAMETER Resolution Differential nonlinearity S/N S/(N + D) ADC common voltage VREF voltage (positive) VREF voltage (negative) ADC output black level calibration code Calibration code resolution SYMBOL RES DNL SN SND VCOM VRP VRN CCAL STCAL CONDITIONS fs = 18 MHz
(fS = 18 MHz, Input signals to ADIN.)
MIN. TYP. 0.6 58 1.0 1.25 0.75 16 1 1 56 1.1 1.35 0.85 MAX. 10 1.0 UNIT bits LSB dB dB V V V LSB LSB LSB 2 NOTE 1
1.2 1.45 0.95 127 127
NOTES :
1. Non missing code is guaranteed. 2. Black calibration period (tBKCAL) is specified when the CCAL is from 16 to 127 LSB. Although black level codes of 1 to 15 could be set, tBKCAL is not guaranteed for these codes.
25
IR3Y48A1
Switching Characteristics
(AVDD, DVDD = 2.7 to 3.6 V, AVSS, DVSS = 0 V, TA = -30 to +85C, CL < 10 pF)
PARAMETER Conversion frequency Clock cycle time Clock rise time Clock fall time Clock low period Clock high period SHR pulse width SHD pulse width SHR sampling aperture SHD sampling aperture Data pulse setup Data pulse hold Sampling pulse non-overlap Enable pulse setup Enable pulse hold OUTCK setup OUTCK hold 3 state disable delay 3 state enable delay ADC output data delay SYMBOL fS tCYC tR tF tL tH tWR tWD tDR tDD tSUD tHD tSP tSUE tHE tSUOC tHOC tDLD tDLE tDL1 tDL2 Active/High-Z High-Z/Active 2 35 2 5 1 10 10 0 10 20 20 (30%/70%) AVDD, DVDD (70%/30%) AVDD, DVDD 23 23 11 11 4 4 CONDITIONS MIN. 0.5 55 2 2 TYP. MAX. 18 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 NOTE
NOTE :
1. When SHD is earlier than ADCKfi, assumed positive. (In the above table, SHD must be earlier at least 2 ns than ADCK.)
26
IR3Y48A1
TIMING CHART
tDR CCD
Reference sampling
tDD
tWR
Data sampling
SHR tWD SHD tCYC ADCK BLK OBP CCDCLP ADCLP OUTCK tDL DO0-DO9 tHE tH tL tSUE tHD tSUD tSP
tHOC
tSUOC
This chart is shown when the Mode (1) D8 bit is set to "1", and an external clock is input to the OUTCK pin. When setting D8 bit to "0", the ADCK is used as OUTCK.
27
IR3Y48A1
AD Conversion Timing (At ADIN (ADC) Input [Mode (1) Register D5 = 1])
ADIN : ADC Direct Input
0.7 AVDD ADCK 0.3 AVDD Falling edge N+1 ADC Input N Sampling point 0.7 AVDD OUTCK 0.3 AVDD tDL Digital Output N+4 N+5 N+6
N-6
N-5
N-2
N-1
N
ADCK Inversion
ADCK Rising edge
OUTCK Timing
ADCK
N+1
tHOC
tSUOC
ADC Input
N Sampling point
OUTCK
These figures are shown when the Mode (1) D8 bit is set to "1", and an external clock is input to the OUTCK pin. When setting D8 bit to "0", the ADCK is used as OUTCK.
28
IR3Y48A1
NOTE :
At default condition in ADIN mode, data are sampled at the falling edge of the ADCK clock, and are output at the rising edge of the OUTCK clock. When the data are sampled and are output at the falling edge of the ADCK clock, set ADCK polarity register to "1". (The upper figure on the previous page shows default timing, and the lower left figure on the previous page shows inverted timing.) Delay from data sampling to data output ADCK normal : At [Mode (1) Register D6 = 0] 5.5 clk delay ADCK inversion : At [Mode (1) Register D6 = 1] 6.0 clk delay In ADIN input mode, the above-mentioned register setting is available. At ADIN (PGA) input [Mode (1) Register D5 = 0 & D4 = 1] digital data output is delayed from above timing by 2 clk.
ADCK Clock Waveform
tH
0.7AVDD
0.3AVDD
tR
tF tL tCYC
29
IR3Y48A1
CONTROL INTERFACE TIMING (AVDD, DVDD = 2.7 to 3.6 V, AVSS, DVSS = 0 V, TA = -30 to +85C)
PARAMETER SCK clock frequency SCK clock low level width SCK clock high level width Data setup time Data hold time SCK, CSN rise time SCK, CSN fall time Number of serial data SYMBOL SCYC SLO SHI SSU SH SR SF SNUM 30%/70% 70%/30% 16 CONDITIONS MIN. 40 40 20 20 6 6 TYP. MAX. 10 UNIT MHz ns ns ns ns ns ns pcs
CSN SSU
50%DVDD
SCYC SLO SHI
SH
SCK
50%DVDD
SSU SH
O0 SDATA
O1
A0
D8
D9
50%DVDD
SNUM
Serial I/F Timing
Digital DC Characteristics
(AVDD, DVDD = 2.7 to 3.6 V, AVSS, DVSS = 0 V, TA = -30 to +85C, Measured as a DC characteristics.)
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input "High" leakage current High-Z leakage current SYMBOL VIL1 VIH1 VOL VOH ILIKG IOZ CONDITIONS MIN. 0.7AVDD IOL = 1 mA IOH = -1 mA 0.7DVDD 10 10 0.3DVDD TYP. MAX. UNIT V 0.3AVDD V V V A A NOTE 1
NOTE :
1. Applied to SHD, SHR, ADCK, BLK, OBP, CCDCLP, ADCLP, CSN, SCK, SDATA, RESETN, STBYN and OUTCK.
30
IR3Y48A1
Data Output Sequence
CCD 0 1 2 3 4 5 6 7 8
SHR
SHD
ADCK
OUTCK
BLK
DO0-DO9
Black Level Code
0
1
2
3
Pixel Data Readout Sequence (1) : Conversion Start
CCD (N - 1) SHR (N)
SHD
ADCK
OUTCK
BLK
DO0-DO9
N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1
N
Black Level Code
Pixel Data Readout Sequence (2) : Conversion End
31
IR3Y48A1
Clock Timing Variations by Register Setting
The variations of clock timings when it is inverted by register settings. 1. No inversion (Mode (1) Register D6 = 0, Mode (2) Register D2 = 0; Default) (Upper figure)
2. ADCK inversion (Mode (1) Register D6 = 1, Mode (2) Register D2 = 0) (Lower figure)
CCD
SHR
SHD
ADCK
OUTCK
DO0-DO9
Pulse Control (Default : No Inversion)
CCD
SHR
SHD
ADCK
OUTCK
DO0-DO9
Pulse Control (ADCK Inversion)
32
IR3Y48A1
3. SHR & SHD inversion (Mode (1) Register D6 = 0, Mode (2) Register D2 = 1) (Upper figure) 4. ADCK, SHR & SHD inversion (Mode (1) Register D6 = 1, Mode (2) Register D2 = 1) (Lower figure)
CCD
SHR
SHD
ADCK
OUTCK
DO0-DO9
Pulse Control (SHR & SHD Inversion)
CCD
SHR
SHD
ADCK
OUTCK
DO0-DO9
Pulse Control (ADCK, SHR & SHD Inversion)
33
IR3Y48A1
APPLICATION CIRCUIT EXAMPLE
The following schematic is the reference circuit for system design. Optimize capacitance and resistance according to the system environment.
DOUT CLOCK POWER CHIP DOWN CONTROL ANALOG 0.1 F DIGITAL 36 OUTCK 37 DO0 38 DO1 39 DO2 40 DO3 41 DO4 42 DVSS DIGITAL OUT 0.1 F 43 DVDD 44 DO5 45 DO6 46 DO7 47 DO8 35 RESETN 34 AVDD3 33 AVSS3 32 STBYN 31 CSN
SIO
CONTROL PULSE
30 SDATA
29 SCK
28 OBP
27 CCDCLP
26 BLK
25 ADCLP SHD 24 SAMPLING PULSE
SHR 23 ADCK 22 NC 21 AVSS1 20 0.1 F AVDD1 19
TOP VIEW
4.7 k$ AISET 18 NC 17 MONOUT 16 OBCAP 15 ADIN 14 CCDIN CLPCAP 13 REFIN 0.1 F ADIN 0.1 F 0.1 F MONITOR
48 DO9 AVDD4 AVDD2 AVDD2 AVSS2 AVSS2 9 0.1 F VCOM 10 0.1 F VRN 4 0.1 F VRP 5 0.1 F NC NC 3 0.1 F
1 10 F + 3 V (TYP.)
2
6
7
8
11
12 0.1 F
0.1 F
CCD
34

▲Up To Search▲

Price & Availability of IR3Y48A1

	To Download IR3Y48A1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .